1. Field
Embodiments of the present invention generally relate to an adjustment of write timing in a memory device. More specifically, embodiments of the present invention refer to adjusting the write timing of the memory device based on a training signal.
2. Background
Data communication between a processing unit and a memory device typically involves sending data along signal paths such as, for example, wires and traces. In a memory device with a synchronous interface, the processing unit may transmit a clock signal along with the data signal to the memory device. The clock signal is used to determine when the data signal should be latched by the memory device, thus synchronizing the memory device to the processing unit. For proper data recovery, the memory device must receive the clock signal within a time period that allows the clock signal to sample the data signal (e.g., the clock signal must sample the data signal within a period of time corresponding to a data eye of the data signal). Otherwise, the memory device may not recover the correct data value.
Real-world variations, such as temperature and jitter, can cause attenuation in the transmitted data signal and clock signal from the processing unit to the memory device, thus causing a loss in data signal integrity. This can result in poor or inaccurate data recovery by the memory device. As operating frequencies in computer systems increase, a need arises to transmit data more rapidly from the processing unit to the memory device. Accordingly, the memory device not only needs to sample data at a faster rate, but also needs to sample the data at the proper time.